Renesas Develops Write Technologies for Embedded STT-MRAM Significantly Reducing MCUs Power Consumption in IoT Applications

On a 20-megabit (Mbit) test chip with embedded MRAM memory cell array in a 16 nm FinFET logic process, a 72 percent reduction in write energy and a 50 percent reduction in the voltage application time were confirmed.

The new technologies are: 1) A self-termination write scheme with slope pulse application, in which the write pulse is automatically and adaptively terminated due to write characteristics of each memory cell; 2) A write sequence to optimize the number of bits, to which write voltage is applied simultaneously. Combined, these technologies make it possible to reduce the power consumption and increase the speed of write operations.

Renesas presented these achievements on December 13 at the 2021 IEEE International Electron Devices Meeting (IEDM), held between December 11 and 15 in San Francisco.

With the accelerated spread of IoT technology in recent years, there has been strong demand for reduced power consumption in microcontroller units (MCUs) used in endpoint devices.

MRAM requires less energy for write operations than flash memory, and is thus particularly well suited for applications with frequent data updates.

However, as demand for data processing capability surges for MCUs, the need to ameliorate the trade off between performance and power consumption increases. Therefore, further power consumption reduction remains a pressing issue.