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energetica-india-57_asiapowerweek

Figure 5: Loss reduction of 50 percent is feasible even with IGBT like dv/dt’s operating at 5kHz. Obviously, the loss reduction will be even higher in applications where there is no dv/dt limitation and at much higher switching frequencies. This is common in DC-DC boost or buck/boost topologies providing the benefit of smaller, lighter and lower cost magnetic components. Various studies have already proven that – even with more expensive power switches – the bill of material can be reduced over a wide spectrum of applications. This number of applications will increase over the mid-term time frame based on the anticipated cost reduction over time for SiC based components. The objective for a SiC transistor design is for the most parts to achieve the lowest area specific on-resistance. This is quite logical, since this parameter defines cost and also indirectly the remaining dynamic losses which are caused by chip capacitance values. The smaller the die for a given resistance, the lower the capacitance values. The high defect density is reflected in various idiosyncrasies or traits of SiC MOS based devices. One example is a weak transconductance in comparison to silicon based power MOSFETs, combined with a low threshold voltage. Another effect is a non-physical temperature behavior of the on-resistance. Physics indicates that the Ronwill typically increase at higher temperatures. Components available today sometimes show zero or even negative temperature dependence. This is due to the fact that the defect related resistance contribution has a negative temperature coefficient and thus, a different temperature behavior is observed. The less the Ron increases with temperature, the higher the impact of channel defects on the device performance. A drop of the defect related resistance contribution can be effectively achieved only by increasing the applied field across the oxide in on-state above values being usually used in silicon based MOS power devices. Since high fields across the oxide in the on-state can potentially accelerate the blocking capability wear out it can be deemed a long term reliability risk. The overall goal is to combine the low Ron-potential offered by SiC with an operational mode where the part remains inside the well-researched safe oxide field conditions. In the on-state this can be achieved by moving away from the planar surface, with its high defect density, towards other, more favorable surface orientations. MOS channels on the so called a-face of SiC offer a factor of at least ten times lower defect densities. For this reason, one possible approach is to use a TRENCH based structure, similar to many modern silicon power devices. Beside the low channel resistance the cell density in such structures can be naturally higher than in planar structures, ending up in a more effective material utilization. Additionally, this would lead to a lower area specific on-resistance. However, in Trench-based components the field stress on the oxide at Trench corners is a critical issue and, especially in SiC, this can be a show stopping argument. This semiconductor chip is proposed to use an about ten times higher electric field compared to Si solutions. There are various possibilities in place to realize an effective shielding of the critical areas, e.g. by deep pn elements. In contrast to the on-state dilemma in the DMOS, the off-state challenge can be addressed by an ingenious design. A powerful SiC switch offering a proven and established ruggedness similar to silicon based components will have a bright future in power electronics applications – even if new challenges are attached to the new technology. In the beginning, there will have to be additional efforts to utilize the technology in the best and most effective way. Challenges include EMI topics arising from faster switching or cooling challenges caused by much higher power densities. The latter are inevitable and combined with the chip shrink which will not be offset by the expected loss reduction. To enable a faster penetration of the SiC transistor technology it is beneficial to address these valid concerns. In this regard, it is essential to partner with customers to minimize any design and implementation processes made necessary by the new technology. Figure 6: SiC switch market 1kW- 500kW @ 10kHz-MHz. It is axiomatic that new semiconductor technologies will be the key enabler to meet the increasing demands for improved power density and efficiency of applications based on power semiconductors. However, the replacement of silicon based components will not be a matter of the next coming years. Instead, wide band gap technologies are able to complement silicon based solutions, especially where they can open up new application niches which cannot be addressed by current technologies. SiC is seen here as the major innovation for industrial power applications targeted at components with blocking voltages above 100V and power ratings up to several hundreds of kilowatt as shown in figure 6. After the successful market introduction of SiC diode technologies, SiC based transistors will be the next major step. By now much higher levels of performance are expected from the wide bandgap material. For a fast market acceptance, ruggedness and system oriented product features are key elements �� SOLAR POWER 24 energetica INDIA · MAY | JUN16


energetica-india-57_asiapowerweek
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